1. Field of the Invention
This invention relates to field effect transistors, and more particularly to transistor structures of the type known as insulated gate field effect transistors.
2. Description of the Prior Art
Recently, various efforts have been made to increase the drain breakdown voltages of insulated gate field effect transistors (hereinafter, briefly referred to as MIS-FET's), and some kinds of high voltage MIS-FET's have been obtained. In improving the high breakdown voltage of the MIS-FET in the prior art, it has been known to be effective if the offset gate structure with an ion-implanted additional channel (or a resistor region) is employed. (Proceedings of the 6th Conference on Solid State Devices, Tokyo, 1974, Supplement to the Journal of Japan Society of Applied Physics, Vol. 44, 1975, pp. 249-255)
FIG. 1 of the accompanying drawings shows a cross section of the high voltage MIS-FET with the ion-implanted offset gate structure.
The MIS-FET in FIG. 1 is a P-channel MIS-FET taken as an example. Numeral 1 designates an N-conductivity type semiconductor substrate. Numerals 2 and 3 designate highly doped P-conductivity type drain and source regions, respectively. Numeral 5 indicates a gate electrode, and numerals 6 and 7 indicate a source electrode and a drain electrode, respectively. Shown at 8 is a silicon dioxide (SiO.sub.2) film. A resistor region 4 having the same conductivity type as that of the drain region 2 is extended and formed from the drain region 2 to underneath an end of the gate electrode 5 in order to lower the strength of an electric field at the end part of the gate electrode 5 as lies on the side of the drain region 2 and to thus enhance the drain breakdown voltage.
With the structure of FIG. 1, however, the reduction of the field strength at the end of the gate electrode is not satisfactory under the influence of the process of charging onto the SiO.sub.2 film 8 overlying the portion of the resistor region 4. In order to solve this drawback, there has been developed a method wherein, as illustrated in FIG. 2 or FIG. 3, the source electrode 6 is extended on the SiO.sub.2 film 8 to an intermediate part of the drain region 2 or the resistor region 4 and it is used as a field plate (electric field moderating electrode) [Japanese Laying-open of Patent Application No. 50-114182 (laid open Sept. 6, 1975), No. 52-65682 (laid open May 31, 1977)]. Another example of the source field plate (SFP) has been known from Japanese Laying-open No. 51-93878 (laid open Aug. 17, 1976).
The field plate shown in FIG. 2, however, incurs a field crowding to an end part of the drain region 2 as lies on the side of the gate electrode 5. Accordingly, it conversely presents a lowering of the breakdown voltage to the drain region. On the other hand, when the field plate is confined up to the intermediate part of the resistor region 4 as shown in FIG. 3, the degradation of the drain breakdown voltage can really be prevented. Disadvantageously, however, part of the resistor layer 4 is prone to be affected by the process of charging onto the insulating film 8, and the fluctuations of characteristics are easily brought about.